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System-Level Validation

This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures.  Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions.  The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

  • Provides a comprehensive introduction to system-level validation
  • Describes high-level modeling using SystemC, UML and transaction-level models
  • Includes coverage of high-level modeling and directed test generation techniques as well efficient validation methodology using directed tests and assertions
  • Shows how to assure consistency between models with test/assertion refinement and reuse techniques across different levels of abstraction

Table of Contents
Chapter 1. Introduction
Chapter 2. Modeling and Specification of SoC Designs
Chapter 3. Automated Generation of Directed Tests
Chapter 4. Functional Test Compaction
Chapter 5. Property Clustering and Learning Techniques
Chapter 6. Decision Ordering Based Learning Techniques
Chapter 7. Synchronized Generation of Directed Tests
Chapter 8. Test Generation Using Design and Property Decompositions
Chapter 9. Learning-Oriented Property Decomposition Approaches
Chapter 10. Directed Test Generation for Multicore Architectures
Chapter 11. Test Generation for Cache Coherence Validation
Chapter 12. Reuse of System Level Tests for Implementation Validation
Chapter 13. Conclusion

Book Details

  • Hardcover: 268 pages
  • Publisher: Springer (September 2012)
  • Language: English
  • ISBN-10: 1461413583
  • ISBN-13: 978-1461413585
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